Version history

v8.8 (Jan 2024)

v8.79 (Dec 2023)

v8.77 (March 2023)

  • Rules defined in Constraint Editor (CE) persists in <design>.rules and reloads automatically
  • Class_class rules defined in CE are now fully accounted durign AR
  • Group of fromto timing rules defined in CE are now fully accounted during in AR
  • Stricter adherence to class_class and class_class layer_rules

v8.75 (March 2023)

  • Improved handling of designs with 2 mixed layer type
  • Continuous improvements to completion rate and routing quality

v8.71 (Jan 2023)

  • Stricter adherence to use_layer rules and T-junction rule
  • Added “report tjs” to report number of t-junctions per net

v8.70 (Dec 2022)

  • Yet more improvements to completion rate and routing quality

v8.62 (Aug 2022)

  • Improved load time in presence full polygon pouring
  • Improvements to completion rate and routing quality

v8.60 (June 2022)

  • Accurate min length meandering with chamfered corners
  • Added File/Recent DO files to recall last 10
  • Area rules support during diff pair routing
  • Prevent occasional samenet violations during track meandering
  • Fixed crash in fromto editor with fast.dsn tutorial
  • Improved accuracy of timing fixers when reaching target length

v8.54 (May 2022)

  • Bug fixes related to diff pair routing

v8.45 (March 2022)

  • Support for polygonal regions
  • Improved QOR for differential pair autorouting








v8.40 (Jan 2022)

  • Import of prerouted differential pairs containing arcs






v8.30 (Sept 2021)

  • Differential pair autorouter supports pair via insertion










v8.20 (May 2021)

v8.06 (Oct 2020)

  • Licensing update for MacOS

v8.05 (Sept 2020)

  • Routing Engine: A new push and shove routing pass is now applied automatically on highly congested boards to resolve spacing violations more quickly than by rerouting nets.
  • MultiRouting Strategy: Provides an easy method to define and run multiple routing strategies within the same session.
  • Advance Routing Strategy: Electra includes a built-in TCL interpreter with DO file extensions. You can develop a routing strategy with high level programming language features such as for-loop, test conditions, file IO, etc…


v7.98 (Feb 2020)

  • Improved differential pair autorouter, no more conflicts at pins to gather point

v7.91 (Dec 2019)

  • Improvement of fanout from polygonal pad shapes
  • Reduced memory leaks on large designs
  • Improved neck down algorithm

v7.86 (April 2019)

  • Added constraints at the padstack level:
    PCB < Layer < Class < Class_layer < Group_set < Group_set_layer < Net < Net_layer < Group < Group_layer < Class_class < Class_class_layer <  Padstack < Region

v7.68 (Jan 2019)

  • Further tweaks and improvement to completion rate.
  • Ability to save/restore new color settings.

v7.67 (Dec 2018)

  • Constraints editor is now mode-less, auto-syncing with selected net and remembers tab selection while browsing the constraints
  • Show selected ratline, excluding others, to reduce display clutter
  • Improved navigation with conflict browser
  • Fixed bug causing crash on some design (introduced in 7.62)
  • Reduced memory footprint on multiple design loads

v7.60 (Oct 2018)

  • Better handling of embedded keepouts in components
  • Matching rules by absolute or ratio tolerance
  • Handle group/group_set redefinition
  • Improved Timing report spreadsheet
  • Added Diff pair by wires with different gap
  • Auto save and restore of the editor for design constraints
  • Improved pin tapering, no less that PCB default width
  • Clean handling of aborting/closing the main app window while autorouting
  • Eagle v9 tested
  • KiCAD v5 tested
  • Linux build available

v7.35 (June 2018)

  • New BGA autorouter. The fanout command auto-detects BGA component and generates “dogbone” segment-via with escape direction by quadrant.

  • Fanout escaping at 45 degrees on rotated components

  • Overriding of the use_layer rule when layers are unselected for routing.

Scenario 1:

Designer wants differential pair nets on layer 4 and 5 and no other nets are allowed to be routed on those layers. Unselect 4 & 5 and assign a use_layer rule for 4 & 5 to the differential pair nets.

Scenario 2:

Let “don’t care” nets to be routed on outer layers but minimizes them on those layers.

  1. Unselect outer layers (direction layer off) no routing is allowed
  2. Put “don’t care” nets in Class “dontcare”
  3. Class use_layer rule TOP & BOTTOM (Class overrides Layer unselect)
  4. Tax layer TOP & BOTTOM to ‘3’
  • Optimization of the hierarchical clearance rules internal handling. This leads to faster routing and improved completion in presence of complex hierarchical clearance rules.
  • Interactive “Recorner selection” will now perform a full miter, generating longer diagonal routes.
  • Added “selected” option to protect/unprotect commands
  • Better handling of clearance to area/keepouts across multi-layers
  • Showing full graphic details during autorouting (ratsnest, vias, etc…)
  • Improved Auto-zoom of selected items

v7.22 (April 2018)

  • Improved syntax checking of lock/unlock/protect/unprotect commands
  • Report lock/protect status during mouse hovering of pad/via/track

v7.21 (April 2018)

  • Router engine tuning for high density designs
    Continuous refinements of the router engine to improve completion rate and quality of results of large test designs.

Constraints Editor:
New tab to control TAX factors to apply to router costs
DO file output of all defined classes and groups definition, even the one with no assigned rule
Fixed Layer buried_via_gap rule overwriting PCB smd_to_turn_gap
Fixed cases of partial rule output to DO file
Missed stub length on DO file output
Allow input of zero grid value

    • Better handling of TCL break when interrupting a routing script
    • Fixes to Constraint Rules dialog box generating DO file (representation of same net clearance type)
    • Updated User’s guide
    • Updated Eagle ULP (see PCB_to_DSN.ulp v3.0)
    • Help/About includes a link to the latest version

GUI related:
New icon in layer panel to distinguish power/gnd planes
Mouse based selection of component with their attached wires
Mouse hover to show component details
Complete sync of crossing/drc display against various panels
Default power/gnd planes ratsnest display is OFF to minimize clutter

v7.10 (Feb 2018)

  • Automatic neck down of fat tracks at pin.
    By default, fat tracks that are in conflict at pins are now necked down by a max of 30% of their width.
    A command is available to change the “neck_down” factor, the syntax is neck_factor <value>.
    The <value> factor can range between 0 and 1;  0.5 means that 50% less width is allowed.
    After a routing pass, the conflicts are analyzed and “neck down” is applied if pin spacing conflicts are present.
  • Eagle ULP v3.1
    Full power/ground planes are now set by default

    Eagle plugin install doc


v7.04a (Jan 2018)

  • Linux build available from the download section, including a demo version.
  • DSN parser was protecting vias requiring an extra step for “unroute all”; not anymore.
  • Costs defined by name (low, forbidden…) are now saved correctly.
  • Support for class_class with post defined class names and net names (Pulsonix DSN).

v7.01 (Jan 2018)

  • User defined “from-to” for redefining the net topology.

select fromto U1-4 P2-10

  • New general purpose single layer no-via router.

setr active_layer TOP

  • Controlled flow to route decoupling capacitor with tracks and the rest with via to planes.

select fromto U1-4 P2-10
select fromto S2-14 P2-12
setr active_layer TOP
unit mm
rule pcb  (clearance 0.254 (type smd_to_turn_gap))
### Single layer detail router
rule pcb  (clearance -1 (type smd_to_turn_gap))
protect selected
unselect all wires
### Regular router, the power type nets will be power-routed to planes
route 5
clean 2
recorner diagonal

  • New “gloss” command to review existing routes to remove extra bends and redundant vias without rerouting like “clean”


  • New report tab in log windows with a spreadsheet view of sortable net routing values: